The present invention relates generally to integrated circuit power management, and more particularly to methods of monitoring power supply quality and adjusting integrated circuit power usage correspondingly.
Modern integrated circuits (ICs) are used in a variety of environments. In some of these environments, e.g., building control and management facilities, large circuit boards or electronic systems such as supercomputers, and vehicle distributed sensor and control systems, the power supply voltage supplied to the ICs can be compromised by a number of factors, such as the distance of the ICs from the power supply source and the number of other ICs in the general vicinity of a specific integrated circuit to be powered, the topology of the power supply distribution network (e.g., point-to-point or star), and the states of the various ICs.
The state of an IC can determine the amount of power it draws. For example, a microprocessor that is in an idle state may draw less power than one that is actively doing calculations. A wireless transmission IC that is attempting to establish a connection (e.g., with a wireless hub or cellular radio tower) typically engages in power ranging, which may draw more power from a power supply than when the IC is either not transmitting or has already acquired a nearby connection.
Additionally, an IC that is powering up may draw more power initially than it does during its steady state operation. Accordingly, a well-known problem associated with IC power management in systems that include many ICs is managing the simultaneous startup of a number of ICs at the same time.
FIG. 1 is a block diagram of a typical electronics system 100 that includes multiple ICs. The system 100 includes a power supply 110, a power distribution network 120, and a plurality of ICs, such as the integrated circuit 130. In operation, the power supply 110 provides power to the network 120, which in turn provides the power to the integrated circuits, such as the integrated circuit 130.
The power supply 110 may be centralized or distributed and may be singled ended or differential. The power distribution network 120 may be a point-to-point, mesh, grid, star, or other topology. In general, the power distribution network 120 will exhibit resistive, inductive, and capacitive properties as will the ICs.
As a result, when power is applied to the system 100, the integrated circuit 130 might not immediately see the full voltage of the power supply 110 but rather will see a gradual rise in the voltage as capacitive elements are charged through resistive elements of the power distribution network 120. Inductive elements may also contribute to ringing and/or overshoot voltages, particularly immediately following the turning on of the power supply 110. Some power supplies are designed with inrush current limiting circuitry to “slow start” systems for these and other reasons.
FIG. 2 is a signal timing diagram 200 associated with signals within an IC (such as the IC 130 of FIG. 1) as a function of time and supply voltage. The timing diagram 200 depicts on the vertical axis (a) a voltage level VDD 205 in the upper portion of the diagram 200, as well as, in the lower portion, (b) a power-on reset low-voltage detect (POR_LVD) signal 210 and (c) an overall IC reset signal /RESET 215. Time is shown to increase from left to right.
The upper portion of the timing diagram 200 also shows several reference voltages. The timing diagram 200 shows (a) a POR trigger level (PTL) 220, (b) an LVD falling trigger level (LFTL) 225, (c) and an LVD rising trigger level (LRTL) 230.
VDD initially starts out very low, as depicted at the left hand side of the timing diagram 200, but as time passes, VDD starts to increase. VDD first crosses the reference voltage PTL 220 at the time 235. At this voltage level, the IC 130 has enough power to operate basic circuits such as band-gap references and other threshold detectors but full functionality is disabled by the /RESET signal 215 being held low.
As more time passes, VDD crosses the LRTL 230 at the time 240. This crossing triggers the power on reset low voltage crossing detection mechanism for the IC 130, causing the POR_LVD 210 to de-assert and the IC to start a countdown to full functionality (e.g., a countdown to starting its system clock).
At the time 245, the timer expires (e.g., a counter that is clocked by an internal power-up clock overflows) and the signal /RESET is de-asserted (i.e., is driven high) allowing full operation of the IC 130 to start.
However, in a typical scenario where the IC 130 is far from the power supply 110, is surrounded by other similar ICs, and/or has a high initial startup current requirement, the voltage VDD 205, reaches a peak voltage 250, and then begins to decrease as more current is drawn than the power supply 110 can provide.
In many cases, VDD will drop below the LVD falling trigger level 225 (e.g., as shown happening at the time 255), causing the power-on low-voltage detection circuitry to de-assert the POR_LVD 210 (also shown happening at the time 255), and consequently forcing the assertion of /RESET (at the time 255) leading to the corresponding reset of the integrated circuit 130.
As a result of the reset of the circuit 130, the integrated circuit's clock is stopped, and the integrated circuit halts operation. Similar ICs on the same power distribution network 120 may also be forced back into reset, and the current draw from the power supply 110 will be reduced, and correspondingly VDD may be seen to start rising again (e.g., as illustrated at the point 260).
Once VDD again reaches the LRTL 230 at the time 265, the POR_LVD 210 is de-asserted (270), the timer again starts running, and the IC 130 is poised to repeat the potentially infinite cycle of (a) coming out of reset (i.e., de-asserting /RESET at the time 275), (b) drawing too much current, and (c) forcing a low voltage threshold crossing at the time 280, and (d) leading to reassertion of /RESET at the time 285.
Thus, it would be advantageous to be able to supply power to multiple ICs in a system without causing inadvertent resets in the ICs.